working system

Go_Board_Constraints.pcf

+# ##############################################################################
+
+# iCEcube PCF
+
+# Version:            2014.12.27052
+
+# File Generated:     Apr 27 2015 09:46:33
+
+# Family & Device:    iCE40HX1K
+
+# Package:            VQ100
+
+# ##############################################################################
+
+### Main FPGA Clock
+set_io i_Clk 15
+
+### LED Pins:
+set_io o_LED_1 56
+set_io o_LED_2 57
+set_io o_LED_3 59
+set_io o_LED_4 60
+
+## Push-Button Switches
+set_io i_Switch_1 53
+set_io i_Switch_2 51
+set_io i_Switch_3 54
+set_io i_Switch_4 52
+
+### 7 Segment Outputs
+set_io o_Segment1_A 3
+set_io o_Segment1_B 4
+set_io o_Segment1_C 93
+set_io o_Segment1_D 91
+set_io o_Segment1_E 90
+set_io o_Segment1_F 1
+set_io o_Segment1_G 2
+set_io o_Segment2_A 100
+set_io o_Segment2_B 99
+set_io o_Segment2_C 97
+set_io o_Segment2_D 95
+set_io o_Segment2_E 94
+set_io o_Segment2_F 8
+set_io o_Segment2_G 96
+
+## UART Outputs
+set_io i_UART_RX 73
+set_io o_UART_TX 74
+
+## VGA Outputs
+set_io o_VGA_HSync 26
+set_io o_VGA_VSync 27
+set_io o_VGA_Red_0 36
+set_io o_VGA_Red_1 37
+set_io o_VGA_Red_2 40
+set_io o_VGA_Grn_0 29
+set_io o_VGA_Grn_1 30
+set_io o_VGA_Grn_2 33
+set_io o_VGA_Blu_0 28
+set_io o_VGA_Blu_1 41
+set_io o_VGA_Blu_2 42
+
+## PMOD Signals
+set_io io_PMOD_1 65
+set_io io_PMOD_2 64
+set_io io_PMOD_3 63
+set_io io_PMOD_4 62
+set_io io_PMOD_7 78
+set_io io_PMOD_8 79
+set_io io_PMOD_9 80
+set_io io_PMOD_10 81

bcd_to_dice.vhd

+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity bcd_to_dice is
+    port (
+        bcd     : in    std_logic_vector(2 downto 0);
+        leds    : out   std_logic_vector(6 downto 0)    := (others => '0')
+    );
+end bcd_to_dice;
+
+architecture rtl of bcd_to_dice is
+begin
+
+    process(bcd) is
+    begin
+
+        leds(0) <= bcd(2) or bcd(1);
+        leds(1) <= bcd(2);
+        leds(2) <= bcd(2) and bcd(1);
+        leds(3) <= bcd(2) and bcd(1);
+        leds(4) <= bcd(2);
+        leds(5) <= bcd(2) or bcd(1);
+        leds(6) <= bcd(0);
+
+    end process;
+
+end architecture;
\ No newline at end of file

dice_sbt.project

+[Project]
+ProjectVersion=2.0
+Version=Lattice Semiconductor Corporation iCEcube - Release: 2020.12.27943 - Build Date: Dec 10 2020 18:03:29
+ProjectName=dice
+Vendor=SiliconBlue
+Synthesis=lse
+ProjectVFiles=bcd_to_dice.vhd=work,number_generator.vhd=work,top_level.vhd
+ProjectCFiles=
+CurImplementation=dice_Implmnt
+Implementations=dice_Implmnt
+StartFromSynthesis=yes
+IPGeneration=false
+
+[dice_Implmnt]
+DeviceFamily=iCE40
+Device=HX1K
+DevicePackage=VQ100
+DevicePower=
+NetlistFile=dice_Implmnt/dice.edf
+AdditionalEDIFFile=
+IPEDIFFile=
+DesignLib=dice_Implmnt/sbt/netlist/oadb-top
+DesignView=_rt
+DesignCell=top
+SynthesisSDCFile=dice_Implmnt/dice.scf
+UserPinConstraintFile=
+UserSDCFile=
+PhysicalConstraintFile=Go_Board_Constraints.pcf
+BackendImplPathName=
+Devicevoltage=1.14
+DevicevoltagePerformance=+/-5%(datasheet default)
+DeviceTemperature=85
+TimingAnalysisBasedOn=Worst
+OperationRange=Commercial
+TypicalCustomTemperature=25
+WorstCustomTemperature=85
+BestCustomTemperature=0
+IOBankVoltages=topBank,2.5 bottomBank,2.5 leftBank,2.5 rightBank,2.5
+derValue=0.701346
+TimingPathNumberStick=0
+
+[lse options]
+CarryChain=True
+CarryChainLength=0
+CommandLineOptions=
+EBRUtilization=100.00
+FSMEncodingStyle=Auto
+FixGatedClocks=True
+I/OInsertion=True
+IntermediateFileDump=False
+LoopLimit=1950
+MaximalFanout=10000
+MemoryInitialValueFileSearchPath=
+NumberOfCriticalPaths=3
+OptimizationGoal=Area
+PropagateConstants=True
+RAMStyle=Auto
+ROMStyle=Auto
+RWCheckOnRam=False
+RemoveDuplicateRegisters=True
+ResolvedMixedDrivers=False
+ResourceSharing=True
+TargetFrequency=
+TopLevelUnit=
+UseIORegister=Auto
+VHDL2008=False
+VerilogIncludeSearchPath=
+
+[tool options]
+PlacerEffortLevel=std
+PlacerAutoLutCascade=yes
+PlacerAutoRamCascade=yes
+PlacerPowerDriven=no
+PlacerAreaDriven=no
+RouteWithTimingDriven=yes
+RouteWithPinPermutation=yes
+BitmapSPIFlashMode=yes
+BitmapRAM4KInit=yes
+BitmapInitRamBank=1111
+BitmapOscillatorFR=low
+BitmapEnableWarmBoot=yes
+BitmapDisableHeader=no
+BitmapSetSecurity=no
+BitmapSetNoUsedIONoPullup=no
+FloorPlannerShowFanInNets=yes
+FloorPlannerShowFanOutNets=yes
+HookTo3rdPartyTextEditor=no
+

number_generator.vhd

+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity number_generator is
+    generic(
+        GC_SEED : std_logic_vector(15 downto 0)
+    );
+    port (
+        clk         : in std_logic;
+        rst         : in std_logic;
+        en          : in std_logic;
+        rand_num    : out std_logic_vector(2 downto 0) := (others => '0')
+    );
+end number_generator;
+
+architecture rtl of number_generator is
+    signal currstate, nextstate : std_logic_vector(15 downto 0);
+    signal feedback             : std_logic;
+begin
+    process (clk)
+    begin
+        if(rst = '1') then
+            currstate <= GC_SEED;
+        elsif rising_edge(clk) then
+            
+            if(en = '1') then
+                currstate <= nextstate;
+            end if;
+
+        end if;
+    end process;
+
+    feedback <= currstate(4) xor currstate(3) xor currstate(2) xor currstate(0);
+    nextstate <= feedback & currstate(15 downto 1);
+    rand_num <= currstate(2 downto 0);
+    
+end architecture;
\ No newline at end of file

top_level.vhd

+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity top is
+    port (
+        i_Clk        : in std_logic;
+        i_Switch_1   : in std_logic;
+        i_Switch_2   : in std_logic;
+        io_PMOD_1    : out std_logic;
+        io_PMOD_2    : out std_logic;
+        io_PMOD_3    : out std_logic;
+        io_PMOD_4    : out std_logic;
+        io_PMOD_7    : out std_logic;
+        io_PMOD_8    : out std_logic;
+        io_PMOD_9    : out std_logic
+        --LEDS        : out std_logic_vector(6 downto 0) := (others => '0')
+    );
+end top;
+
+architecture rtl of top is
+
+    signal random_num : std_logic_vector(2 downto 0);
+    signal leds : std_logic_vector(6 downto 0);
+
+    signal generate_rand_num : std_logic;
+    signal output_rand_num : std_logic_vector(2 downto 0);
+
+    signal clk : std_logic;
+    signal rst : std_logic;
+    signal button  : std_logic;
+
+    type t_lfsr_state is (IDLE, DEADGAP, GENERATE_NUMBER);
+    signal state        : t_lfsr_state := IDLE;
+
+    signal counter : std_logic_vector(3 downto 0);
+    signal button_r : std_logic;
+
+begin
+
+    clk <= i_Clk;
+    rst <= i_Switch_2;
+    button <= i_Switch_1;
+
+    process (clk, rst)
+        variable v_generate_rand_num : std_logic;
+    begin
+
+        if(rst = '1') then
+            state       <= IDLE;
+            generate_rand_num <= '0';
+            leds <= (others => '0');
+
+
+        elsif rising_edge(clk) then
+
+            v_generate_rand_num := '0';
+            button_r <= button;
+
+            case state is
+                -------------------------------------------------------------------------------
+                when IDLE =>
+                    -- Wait for button to be pressed
+                    -------------------------------------------------------------------------------
+                    if (button='0' and button_r='1') then
+                        state <= DEADGAP;
+                    end if;
+                
+                -------------------------------------------------------------------------------
+                when DEADGAP =>
+                    -- A counter for debouncing button
+                    -------------------------------------------------------------------------------
+                    counter <= std_logic_vector(unsigned(counter) + 1);
+                    if (counter = "1111") then
+                        v_generate_rand_num := '1';
+                        state <= GENERATE_NUMBER;
+                        counter <= (others => '0');
+                    end if;
+                -------------------------------------------------------------------------------
+                when GENERATE_NUMBER =>
+                    -- Generate number
+                    -- If number is 0 or 7, generate a new one
+                    -------------------------------------------------------------------------------
+                    v_generate_rand_num := '1';
+                    
+                    if (not (random_num = "000" or random_num = "111")) then
+                        output_rand_num <= random_num;
+                        state <= IDLE;
+                    end if;
+
+                -------------------------------------------------------------------------------
+                when others =>
+                    -------------------------------------------------------------------------------
+                    state <= IDLE;
+                    
+            end case;
+
+            generate_rand_num <= v_generate_rand_num;
+        end if;
+    end process;
+
+    tallgenerator : entity work.number_generator
+        generic map(
+            GC_SEED => X"FACE"
+        )
+        port map(
+            clk         => i_Clk,
+            rst         => i_Switch_2,
+            en          => generate_rand_num,
+            rand_num    => random_num
+        );
+
+    dekoder : entity work.bcd_to_dice
+        port map(
+            bcd        => output_rand_num,
+            leds(0)    => io_PMOD_1,
+            leds(1)    => io_PMOD_2,
+            leds(2)    => io_PMOD_3,
+            leds(3)    => io_PMOD_4,
+            leds(4)    => io_PMOD_7,
+            leds(5)    => io_PMOD_8,
+            leds(6)    => io_PMOD_9
+        );
+
+end architecture;
\ No newline at end of file